Talk:Pentium M

Yes, a very interesting design indeed, Adam. A P-III core, with a longer pipeline to allow higher clockspeeds and yet (amazingly) IPC higher than the P-III! The much-enlarged caches no doubt have a lot to do with that. Intel's PR fools are doing their best to pretend it's a completely new design (because they don't want to admit that the P-4 just isn't cutting the mustard in notebooks, or that they are using the ten-year-old P-Pro/II/III core yet again) but it ain't. It will be very interesting to see what Ace's have to say about it. Keep your eye on www.aceshardware.com - Tannin

Well, I'm a HardOCP man myself, where they don't have much interest in nancy pursuits like laptops ;). But yes, interesting stuff. --AW

Ace's neither, but I figure the unusual architecture, not to mention the "return of the undead factor" in seeing the P-6 core back yet again, will make it too interesting for them to ignore. Though how they are going to get one into a suitable desktop platform to allow sensible testing, I don't know. -- T

Testing I've seen so far has just tried to pit Pentium M notebooks against vaguely comparable P4 notebooks. Which is kind of inaccurate. :\ --AW

Quite so. Notebooks are tricky. Actually, I just cancelled a notebook order because of the Pentium M - I was going to get one of the last of the (P-III based) 1200MHz Celerons because I didn't want one of those over-rated, power-hungry P-4s or P-4 family Celerons, but then I decided to wait a little longer and get a Centrino-based one instead. Nothing fancy - I have desktops for hosepower when I need it - just a portable Wiki editing machine I can use outside with a long network cable. And seeing as it will be winter here soon and too cold to go outside, I might as well wait six months. :) And now I'm really off-topic. I better stop. Tannin

/me continues recklessly off-topic...well, my rather ancient tiny notebook (Sony Picturebook...mmm) runs a P2-400 for around 1.5 hours battery life. But I don't care, because it's tiny! And it has a WLAN card, too. Mmmm, Wiki editing in bed...=). I'd better stop too! --AW

advertisement perhaps?

"such as the Toradex Midget (95×70×15 millimeters). In conjunction with the Intel 915GM Northbridge, which comprises up to four lanes of PCI Express, the Toradex Midget computer module delivers very high data throughput rates of up to 4 × 2 gigabits per second."

This sounds like a more or less blatent advertisement for this microcomputer. I wouldn't suggest removing the product altogether, but it definitely steals focus from the point of the article, the Pentium M.

It's sufficient to mention the machine, not its dimensions or its Studly(TM) I/O bandwidth. I've left the name in, complete with Wikilink to Toradex, but removed the rest. Guy Harris 01:08, 24 March 2006 (UTC)

huh?? low power or not?

"is it is not a low-power version of the desktop-or"

"Running with very low average power consumption"

which is it?? - Omegatron 13:26, Aug 8, 2004 (UTC)

It's a low power cpu, but not a modified Pentium 4. --Niffux 19:37, 14 Oct 2004 (UTC)

Front Side Bus

The user named 'Denniss' uses different terminology than myself and Intel Corp. to describe the speed of the front side bus (e.g. FSB400 for a 400 MHz FSB). Since these are minor edits, and I don't want to get into a minor edit war, I thought we could discuss it here.

1 Hertz means 1 of anything per second. Now the front side bus of Pentium M is sync'd to a clock on the system board, and the *clock* itself runs at 100 MHz for a Banias Pentium M. However, the Front Side Bus itself can do more than 1 transaction per clock. I believe it is up to 4 transfers per cycle. So while the frequency of the clock is 100 MHz, the frequency that the bus transacts is actually 4 times 100 MHz, or 400 MHz.

Intel describes its FSB speeds in terms of MHz, not FSB400 or FSB800. http://www.intel.com/products/processor/pentiumm/index.htm

Also, I have not come across any English language tech sites like AnandTech, Aces Hardware, or Arstechnica that use 'FSB400' and the like.

Now since I don't want to get into an edit war over this minor matter, I won't change any of the FSBxxx designations, but I would like to know which people believe is the more correct designation (FSB400 or 400 MHz Front Side Bus).

Mhz is a physical specification. Even if the FSB transfers 4 pieces of data this does not make him run at 400 MHz !! This FSB runs at 100 MHz using a QDR-Bus transferring 4 pieces of data per clock cycle, leading to the 400 "Mhz" Marketing FSB. 400 MHz FSB is completely wrong, 100 MHz is the correct term (with added quadpumped, (or QDR) FSB400). --Denniss 12:32, 2005 Jun 13 (UTC)

MHz is not a physical specification. See http://en.wikipedia.org/wiki/Hertz . I quote: "One hertz simply means "one per second" (1 / s); 100 Hz means "one hundred per second", and so on. The unit may be applied to any periodic event" (bolded for emphasis). So while the clock of the bus may run at 100 MHz, if there are 4 transcations (events) per clock, there are 400 million transactions (events)/second, so the 400 MHz specification is accurate. 400 MHz refers to the # of transactions the bus does. - K. Eng

You are wrong again: Hertz is a physical specification - the FSB is clocked at 100 MHz. The FSB transports 4 pieces of data but that does not change the MHz to 400, it remains at 100. The FSB uses some special mechanism to transport this data (at the falling and raising clock signal (achieving DDR) and AFAIK inverted to the clock signal to transport another two pieces of data to achieve QDR), more info on Front side bus. --Denniss 01:25, 2005 Jun 15 (UTC)

http://dictionary.reference.com/search?q=Hertz . "A unit of frequency equal to one cycle per second." By definition 'Hertz' can be a cycle of anything. I don't dispute that the physical clock runs at 100 MHz, but the data transfer rate is still 400 MHz. Again, Hz is not inherently physical by definition (which I have provided two sources), and the vast majority of websites, including Intel's own site, use 400 MHz as the measure of the front side bus speed.

Sorry but you seem to look at the wrong sources. The clock rate is still the same 100 MHz (or 133, 166, 200, 266 MHz). There is no 4x data clock rate because it always happens at the same clock rate. Intel used this 400 "MHz" FSB because it looks better than 100 MHz but 4 pieces of data per cycle (easier for marketing). You have the same with DDR FSB on AMD systems and DDR memory - there is always a physical clockrate but 2 pieces of data are transferred. This does not change a clockrate of 100 MHz to 200 MHz.

The MHz definition on the FSB is always used for clockrate, you can't specify a data rate with MHz because it has no MHz !

Then show some authoritative sources that say that Herts has to be a physical specification. So far, the other person has quoted two sources, while you're keeping your sources to yourself. There's something very fishy about that. It sounds like you don't care about accuracy and you're making up things to push an agenda. Oh, and I've always learned from every science textbook I've read that the frequency of a wave is the amount of waves that pass a certain point in a certain amount of time. Adapting this for computer buses, it would be the amount of data that passes a point on the bus in a certain amount of time. --Jgp 22:42, 18 Jun 2005 (UTC)

It is obvious to me that we probably will not be able to agree. However, I believe the 'FSB400' and the like has to go. Nobody, not AnandTech, Extremetech, Arstechnica, Sandpile, or any of the major English speaking sites use this kind of designation. I think "100 MHz FSB (QDR, 400 MHz effective)" may be an acceptable alternative. It acknowledges that the clock is 100 MHz, but that the bus is capable of 4 transfers per clock - roughly the same effect as a 400 MHz bus that does only one transfer per clock.

I agree with your sentiment, but I'll add that a better phrasing would be "400 MHz FSB (100 MHz quad-pumped)". The effective data rate is far more important than the physical clock (which really doesn't matter and shouldn't even be mentioned, but it seems that some people just can't be satisfied), and should be emphasised. --Jgp 22:42, 18 Jun 2005 (UTC)

For clarity, its common to indicate effective bus speed in Mega Transfers (MT/s) in order avoid confusing it with clock speed.

I'll add some stuff on the Merom core as soon as possible. Lots of new info from the Fall IDF this year.

How do I get my signature to show up?

ah ok... here we go K. Eng

Hi. I have to strongly disagree with guys stating that it is correct to use 400 MHz instead of 100 MHz if there are actually four pieces of data within one cycle. And I will use their own weapon: Hertz - "A unit of frequency equal to one cycle per second." and "The unit may be applied to any periodic event" And the periodic event is the transfer of exactly four pieces of data at a time. It is not the transfer of one piece, simply because you cannot stop after it, you have to transfer the whole quartet (or at least this is the way I believe the bus to work). Transferring one quartet is atomic operation and thus the frequency is the same as the clock frequency, not four times more. - You do not say that the RAM has double frequency if you have dualchannel configuration which (theoretically) transfers twice as much data than single-channel ... --Kavol 18:54, 21 February 2006 (UTC)

I was looking at this and thinking that it would affect the discussion to know exactly how quad pumping works. From my sniffing around, it looks like the FSB takes the shape of a parallel data bus with a clock line alongside. This is the bus as it runs from the CPU across the PCB to some other device. So the clock line on the bus carries a synchronising clock running at 100 MHz. Data words are put on to the data lines with four changes for every clock cycle. So that means that the data words are put through at a rate of 400 million per second. You can bet that the silicon is not magically able to work out when it is a quarter of a way through a cycle and therefore time to put the next data word out. If you are a bit of circuitry looking at a clock signal go by in front of you, waiting for a certain state to occur, you can only reliably pick out two points in each cycle; so you could do double-pumping with no further clocking. But for quad-pumping you are going to need an extra (internal) clock running at each end. You need to be able to pick out four points per cycle of the FSB clock, but you can only pick out two. So you need another clock running at twice the frequency of the FSB clock, accurately phase synchronised with it. So in the CPU and the peer device, you will have a PLL and an internal clock running at twice the FSB clock. You can then reliably pick out two points per cycle on the internal PLL clock signal to give you 400 million points per second. The above is not necessarily how it actually works, but is a reasonable educated hypothesis.

So where does that leave us? Well the normal usage of Hertz is to refer to a periodic cycling thing. That thing should cycle round in a way where the path reaches any distinct state exactly once per cycle, and where each cycle is largely the same as the other cycles, like a swinging pendulum, or a rotating shaft, or an oscillating signal. (Although a pendulum passes all points except the extremes twice, it's travelling in a different direction, so those states are considered distinct.)

In this case although the data are transferred at 400 million words per second, there is no point in the system which has identical cycles occurring 400 million times per second. So it would not be normal usage to talk about "400 MHz". The internal clocks may run at 200 MHz, but they're internal to the CPU and the peer device. The thing that is specified is the FSB, which uses a 100 MHz clock, but the specification says that transfers happen at four carefully-specified (and presumably equally-spaced) points on each clock cycle.

But, the fact that the FSB clock is 100 MHz isn't important in and of itself when thinking about overall bus performance. What is important is the data rate. This needs to take into account the "pumping" factor and the width of the bus. In an environment where the bus width is constant, the important factor is the data word transfer rate.

I think using Hertz is dodgy here. To be correct we probably should say something like 400 megatransfers per second, or 400 Mtransfer/s.

So why does every reference I have seen use MHz? I think what has happened is that originally FSBs operated conventionally with one transfer per clock cycle, so to work out the data rate you multiplied the clock frequency by the bus width. When double- and quad-pumped buses appeared, it was convenient to use an "equivalent" bus clock frequency which could still be multiplied by the bus width to give a figure for data rate comparable to those used for conventional ("single pumped") buses. So the "normal" usage was to subvert the term Hertz to mean transfers per second.

So we are talking about notional "equivalent" bus frequency which is the product of the bus clock multiplied by the pumping factor.

We could summarise this in a form such as: "400 MHz equivalent (100 MHz quad-pumped) FSB".

Any good?

Duckbill 00:53, 23 February 2006 (UTC)

Yonah and Sossaman moved?

I guess I missed the discussion - why was the information for Yonah and Sossaman moved? It seems perfectly relevant to have that information here, and it's not like the new article is long enough to actually justify a whole new page. >Confused!< -4.243.113.215 20:00, 30 December 2005 (UTC)

Perhaps because Intel is using a different brand name for them? I'm not arguing that's right, just that it might be the reason why people moved it. There are separate pages for Pentium 4, Pentium D, Pentium Extreme Edition, etc., even though they have the same architecture. Guy Harris 07:59, 15 February 2006 (UTC)

On a similar note, is there any support for removing Merom and Conroe information from this article (or at least moving them into Intel Core)? They won't be using the Pentium M brand, and they don't even use the same microarchitecture as the Pentium M. Jgp 21:47, 15 February 2006 (UTC)

Sounds good to me.

As for whether Yonah and Sossaman belong here, perhaps there should be a page for the microarchitecture used by Pentium M and Yonah/Sossaman, with Pentium M used for chips using that brand and Intel Core used for chips using that brand, regardless of whether they use the same microarchitecture as Pentium M or use the Intel Next Generation Microarchitecture, just as there are pages for Intel x86 microarchitectures (starting with P6) as well as pages for various brands used for those chips. Guy Harris 21:57, 15 February 2006 (UTC)

The CPUID signature for a Yonah is 0x6EX.

Since when is X a hexadecimal digit?!?? It seems as if someone has been trying to make it look leet (6EX = sex).. I am removing this. Put it back if you can find a reference that proves it.

---

Sorry to sound stupid and everything, but which one is better? Turion or Pentium M? Thanks Number 8 04:23, 21 February 2006 (UTC)

New WP:MOSNUM "policy" re lengths

I went to have a look at WP:MOSNUM. It appears that WP:MOSNUM has recently received a significant large edit from a new user without the normal discussion taking place first. The edit has been reverted by more experienced hands. Discussion is in progress. We might be best off allowing new guidelines to settle for a while before rushing out making changes to pages such as this one. Duckbill 17:48, 10 March 2006 (UTC)

Wrong Year For Release

The P4-M was released in March 2002, not 2003. See Press Release --59.167.194.117 12:36, 15 August 2006 (UTC)

Well, then. I'm glad this article isn't about the Pentium 4-M. jgp ^T_C 13:54, 15 August 2006 (UTC)

image from datasheet copyrighted?

I would like to add pictures of the contacts of two Pentium M variants: A micro-FCPGA with 478 contacts and a micro-FCBGA with 479 contacts. The images would be from pg 29 and 34 of http://download.intel.com/design/mobile/datashts/25261203.pdf (found on page http://developer.intel.com/design/mobile/pentiumm/documentation.htm)

(These pictures would be of interest given that newegg and other sell Pentium M which they say is for socket 478. This is confusing because previously only Pentium 4 were socket 478.) 75.2.59.169 15:05, 21 December 2006 (UTC)

Yes, those images would be subject to Intel's copyright. — Aluvus ^t/c 21:36, 21 December 2006 (UTC)

Could these images be used under the "Fair Use" provision of copyright law? (http://en.wikipedia.org/wiki/Fair_use) 75.2.59.169 15:21, 22 December 2006 (UTC)

Word size not specified.

According to http://en.wikipedia.org/wiki/List_of_Intel_Pentium_M_microprocessors begins by mentioning that these processors are 32 bit processors.

Although it may be redundant, a search for "Pentium M" lands one on this page, so it would be helpful to mention in this document as well that they are 32 bit processors. The word size isn't going to change and so having it mentioned in two places should not introduce concerns about synchronizing information.

JJ Bosch (talk) 20:57, 22 September 2012 (UTC)

Instruction set

The Pentium M does support running in 16-bit real mode, not to mention VM86 and even VME added by the P6 microarchitecture that the Pentium M is based on. (Though VME could be considered an extension and maybe VM86 too since it was added in the 386 which wasn't the first IA32 processor) — Bryce Michael Wilson (Talk) 15:54, 14 February 2024 (UTC)

Should mention developmemt history

Was Designed by an Intel Team in Isreal. Separate from normal Roadmap.

Was a necessary restart after the Pentium 4 line had Hit a wall. 2A01:599:91F:89C5:49FA:6DE7:67ED:C6EB (talk) 21:31, 29 February 2024 (UTC)